DBT 2006 - Call for Participation

CALL FOR PARTICIPATION

ONLY ON-SITE REGISTRATION IS AVAILABLE FOR DBT

Overview -- More Information -- Committees

Overview

Theme
Defect-Based or Data-Based Testing: What’s the difference?

Defective parts are due to either systematic or random manufacturing defects. As new processes with new manufacturing steps evolve and new structures are meanwhile being developed, new defect mechanisms arise. To develop more appropriate fault models, a good understanding of, and a continuous follow-up on defect mechanisms -both systematic and random- is mandatory to support the manufacturability of today's and tomorrows integrated circuits, fueling defect based test approaches. Increasing design complexity as well as the need to better cope with process variability shifts the focus from pass/fail oriented test to data-based test approaches, exploiting information on the neighborhood to support a better decision making. The requirement to distinguish between good and bad parts in a reliable way, taking into account the need to cope with process variability imposes a data-based defect-based test approach.

The IEEE International Workshop on Current and Defect Based Testing (DBT 2006) is aimed at addressing these issues and others related to “Defect-Based or Data-Based Testing: What’s the difference?” Paper presentations on topics related to the workshop’s theme and to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

Test Data Analysis
Data-Mining approaches for Test Data
Transition and Delay Testing Processing
IDDQ and IDDT Testing
Elevated Voltage Testing and Stress Testing
Low voltage Testing
Reliability and Yield
Noise and Cross-talk Testing
Nanometer Test Challenges
Defect Coverage & Metrics
Mixed Current/Voltage Testing
Economics of Defect Based Testing
Fault Localization & Diagnosis
Outlier Identification
Data-Based Testing

More Information

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General Information:

Jim Plusquellic
Dept. of Electrical & Computer Eng.
University of Maryland, Baltimore County
Baltimore, MD 21250, USA
Tel: (410) 455-1349, x-3969(FAX)
E-mail: Plusquel@csee.umbc.edu

Committees

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GENERAL CHAIR
Jim Plusquellic
Univ. of Maryland, Baltimore County

CO-GENERAL CHAIR
Hans Manhaeve
Q-Star Test nv Brugge, Belgium

VICE-GENERAL CHAIR
Duncan (Hank) Walker
Texas A&M Univ., USA

PROGRAM CHAIR
Mehdi Tahoori
Northeastern University, USA

PROGRAM CO-CHAIR
Sankaran Menon
Intel Corporation, USA

FINANCE CHAIR
Sankaran M. Menon
Intel Corporation, USA

PUBLICITY CHAIR
Jaume Segura
UIB Baleares, Spain

ADVISOR
Charles Hawkins
University of New Mexico, USA

STEERING COMMITTEE
Yashwant K. Malaiya (Chair) Colorado State University, USA
Anura Jayasumana Col. State Univ, USA
Joan Figueras, UPC, Barcelona, Spain
Adit Singh, Auburn University, USA
Duncan (Hank) Walker, Texas A&M Univ.

PROGRAM COMMITTEE
Robert Aitken, Agilent Technologies, USA
Tom Barnett, Auburn University, USA
Sreejit Chakravarty, Intel, USA
Anne Gattiker, IBM, USA
Ali Keshavarzi, Intel, USA
Bram Kruseman, Philips, The Netherlands
Martin Margala, Univ. of Rochester, USA
Peter Maxwell, Agilent Technologies, USA
Ed McCluskey, Stanford Univ., USA
Subhasish Mitra, Stanford Univ., USA
Chintan Patel, UMBC, USA
Michel Renovell, LIRMM, France
Andrew Richardson, Lancaster Univ., UK
Marly Roncken, Intel, USA
Rob Roy, Zenesys, USA
Manoj Sachdev, Univ. of Waterloo, Canada
Jerry Soden, Sandia National Labs, USA
Mohammed Tehranipoor, UMBC, USA
Claude Thibeault,Ecole de Tech Sup, Canada
Bapi Vinnakota, Intel Corp., USA
Victor Zieren, Philips Res., The Netherlands

For more information, visit us on the web at: http://www.cs.colostate.edu/~malaiya/dbt.html

The IEEE International Workshop on Current & Defect Based Testing (DBT) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).